1. Field of the Invention
This invention relates to the field of device verification, and in particular, to a system for profiling, checking, optimizing and generating test patterns for verifying functionality of a device.
2. Description of the Related Art
As technology continues to improve, digital electronic products become increasingly sophisticated and present a bigger verification challenge to product designers. A huge expense is incurred in setting up the manufacturing process for constructing a particular product, so designers need to be sure their product design operates correctly before finally implementing it in silicon. Due to the sheer number of components that make up a typical product, verification of the functionality of the overall product is no small task.
Since electronic devices are designed to produce a deterministic set of output signals in response to a given set of input signals, verification at its most fundamental level consists of providing the given set of input signals to the device and comparing the resulting set of output signals to a set of expected output signals. If the device is operating correctly, no mismatch is found.
Complete verification can theoretically be achieved by applying all valid sets of input signals to the device and determining that the output signal sets match the expected signal sets. This is almost always impractical due to the number of valid sets of input signals, particularly in the case of devices with a large number of internal states, e.g. microprocessors. Consequently, the system designer seeks a set of input signals of a tolerable size which can provide a “high-enough” level of verification. How are verification levels measured? What constitutes a “high-enough” level of verification? These questions are still the subject of much debate.
Various traditional methods of obtaining a set of input signals for verification exist. In one method, the device designers arbitrarily generate input signal sets that they believe will exercise the various device components. This method serves well for verifying high-level, obvious operations of the device. In another method, a computer generates a large set of random input signals. This method is undirected and results in inefficient use of computer resources. These two methods are often combined to form a hybrid method, in which the designer-generated input signal sets are augmented by a set of random input signals.
The amount of confidence placed in a device's successful handling of a set of input signals depends on the estimated verification level, i.e. the percentage of complete verification provided by operating on the set of input signals. Verification levels are commonly stated in terms of coverage of some design aspect of the device. It should be noted that while complete verification implies complete coverage of any given device design aspect, the converse is not necessarily true. For example, one coverage measurement is determined from a hardware description language (HDL) code listing used to design the device. This coverage measurement states the percent coverage in terms of the percentage of HDL code lines from the entire code listing that are executed by a simulator in response to the set of input signals. However, since a single HDL code line can often represent a circuit module of moderate complexity, a single execution of that code line falls well short of thoroughly verifying that code module.
Another coverage measurement is determined by monitoring each electrical node in the device and counting the number of nodes that are toggled at least once during application of the set of input signals. The percent coverage is then stated in terms of the percentage of toggled nodes. Again, this falls well short of thoroughly verifying the device since most of the combinations of nodes states go untested. A simple example of a fault that could be missed is a short between adjacent nodes that would prevent proper device operation when the device is expected to place the nodes in different states, but would go undetected by tests that toggle the nodes in synchronization.
Another coverage measurement is determined by simulating faults and counting the percentage of faults that are detected by application of the input signal set. While effective, this measurement method is statistical in nature and requires a substantial amount of computer resources.
Each of these methods attempts to measure the verification level from a hardware perspective; a daunting task due to the sheer number of combinations of node states that can exist in even a relatively simple device. The designer is often left with a choice between a low verification level and an inconveniently large set of input signals.
Verification terminology that is used herein is as follows: The group of input signals applied to a device at a given time instant is an input vector; a sequence of input vectors over consecutive time instants forms an input pattern. Similarly, output signals are referred to in terms of output vector and output pattern. An input pattern and its associated expected output pattern together form a test pattern, although it should be understood that the test pattern can be specified by the input pattern and a method for determining the desired output pattern (e.g. a device simulator). The procedure of running a test pattern includes applying an input pattern to the device and comparing the output pattern from the device with the expected output pattern. Depending on the situation, the device may need to be placed in a specified initial state before the input pattern is applied. Where the test pattern is designed to verify one or more functional aspects of the device, the test pattern is a functional test pattern or sometimes just a functional pattern. A distinction might be drawn between a functional test pattern and a manufacturing test pattern, in that the manufacturing test pattern is designed to verify that the manufacturing process is creating devices with a low defect rate. Nevertheless, some commonality exists, and it is noted that a functional test pattern could serve as a manufacturing test pattern, and vice versa.
Test patterns can comprise an enormous amount of data, in fact the running of some test patterns can last for days. Construction and handling of these test patterns can be difficult and unwieldy. A system infrastructure that provides for uniform handling of test patterns and simplifies the verification process would provide dramatic savings of time and effort, and advantageously reduce the overall cost of device design.